1. Field of the Invention
The present invention relates to a data correction scheme for a flash memory, and more particularly to a method, controller, and a memory device for correcting data bit(s) of at least one cell of the flash memory.
2. Description of the Prior Art
Generally speaking, an error correction code (ECC) processing circuit may be configured within a conventional flash memory controller. The conventional flash memory controller uses the ECC processing circuit to try to correct data bits read out from a flash memory so as to try to obtain correct data bits. When the total bit errors of codeword data can still corrected by the conventional ECC processing circuit, this indicates that the conventional ECC processing circuit is able to effectively correct bit errors of the codeword data and obtains correct data content. However, if the conventional ECC processing circuit is applied to try to correct the bit errors resulted from electric level shift impact caused by previous data writing or other factors, the conventional ECC processing circuit usually will fail since the number of bit errors caused by the electric level shift impact may become more. Accordingly, the conventional ECC processing circuit may not able to effectively correct data bits readout from the flash memory and thus cannot obtain correct data content.